1. Field of the Invention
The present invention relates to techniques for predicting manufacturing yield for integrated circuit fabrication processes. More specifically, the present invention relates to a method and apparatus for predicting manufacturing yield for integrated circuit fabrication processes by considering both systematic and random intra-die variations.
2. Related Art
Dramatic improvements in semiconductor integration circuit (IC) technology presently make it possible to integrate tens of millions of transistors, onto a single semiconductor IC chip. These improvements in integration densities have largely been achieved through corresponding improvements in semiconductor manufacturing technologies, which have recently achieved deep-submicron feature sizes.
On the flip side, the constant drive towards ever-decreasing feature sizes has led to a significant increase in manufacturing cost. One of the main causes of this increase in manufacturing costs is a significant decrease in manufacturing yield due to manufacturing losses. Therefore, it is extremely desirable to be able to predict manufacturing yield at the design stage. This enables corrections and improvements to be made during the design stage to improve the ultimate manufacturing yield.
IC manufacturing processes typically involve complex physical and chemical interactions. Because it is impossible to perfectly control these complex physical and chemical interactions, process parameters associated with these manufacturing processes tend to fluctuate around their nominal values, causing “process parameter variations.” Such process parameter variations can significantly reduce manufacturing yield.
In conventional systems, process parameter variations and the associated yield issues are taken into account, without considering the physical layout of a chip. This methodology is sufficient when the lot-lot, wafer-wafer and die-die variations dominate the overall process parameter variations. However, because of the recent reductions in feature size, intra-die parameter variations at the feature level are becoming increasingly more significant in determining manufacturing yield.
Specifically, a number of systematic intra-die variations have been observed as a function of layout patterns. In particular, two examples are: (1) intra-die critical dimension (CD) variations in the microlithography process and (2) copper (Cu) thickness and oxide thickness variations in the chemical-mechanical planarization (CMP) process. Empirical data shows that systematic intra-die CD and Cu thickness variations due to the layout pattern non-uniformity are becoming comparable to variations caused by lot-lot, wafer-wafer and die-die variations. This is a problem because conventional techniques for predicting yield do not consider these intra-die variations. Intra-die variations have a strong layout dependent component. To account for intra-die variations, it is necessary to look at compensation of the design at the design stage. Hence it is desirable to have a manufacturing yield prediction model.
To reduce the above-mentioned process variations, design for manufacturing/yield (DFM/DFY) technologies, such as: optical proximity correction (OPC), phase shifting mask (PSM), scattering assistant bar and the dummy filling (DF) have been introduced into IC design flows. Additionally, various full-chip simulation tools have been developed to evaluate systematic intra-die variations.
In addition to systematic intra-die variations, random intra-die variations are another important component of total intra-die variations. Specifically, random intra-die variations create random fluctuations of a process parameter at different locations within a die in a random statistical manner.
Furthermore, the random intra-die variations tend to be spatially correlated. Typically, when the lot-lot, wafer-wafer, and die-die random variations dominate the overall random variations, a perfect spatial correlation (˜1) of the random variations across each die can be assumed. However, due to increasing die-size and more-significant random intra-die variations, the spatial correlations of the random variations between two intra-die locations are not perfect, but instead decrease with the distances between the locations. These non-perfect correlations between intra-die locations can strongly affect the total manufacturing yield.
Unfortunately, neither random intra-die variations nor the associated spatial correlations of the random intra-die variations have been taken into account while predicting the IC manufacturing yield.
Hence, what is needed is a method and an apparatus for predicting IC manufacturing yield without the above-described problems.